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this is information on a product in full production. october 2014 docid18211 rev 3 1/29 ALTAIR04-900 off-line all-primary-sensing switching regulator datasheet - production data features ? optoless primary side constant voltage operations ? adjustable and mains-independent maximum output current for safe operations during overload/short-circuit conditions ? 900 v avalanche-rugged internal power section ? quasi-resonant valley switching operation ? low standby consumption ? overcurrent protection against transformer saturation and secondary diode short-circuit ? so16n package applications ? smps for energy metering ? auxiliary power supplies for 3-phase input industrial systems ? ac-dc adapters description the ALTAIR04-900 is a high voltage all-primary- sensing switcher, operating directly from the rectified mains with minimum external parts. it combines a high-performance low voltage pwm controller chip and a 900 v avalanche-rugged power section in the same package. figure 1. block diagram so16n 3.3 v zcd/f b i ff sta rt er source turn - on logic +vi n +v out is ta r t - up internal supply bus vref in te r n . supply bus drain blanking time leb vc c ir e f 2.5 v r s q comp - + - + + - s/h de mag logic gnd s r q ir ef r protection & fe ed for w ar d lo g i c pr o t i ff vc - + 1 v s r q uv l o uv lo pr o t r ff su pp ly & uv l o rfb rz cd rsense rcomp ccomp cr e f 3.3 v zcd/f b i ff sta rt er sta rt er source turn - on logic +vi n +v out is ta r t - up internal supply bus vref in te r n . supply bus drain blanking time blanking time leb leb vc c ir e f 2.5 v r s q comp - + - + - + + - + - s/h s/h de mag logic de mag logic gnd s r q s r q ir ef r protection & fe ed for w ar d lo g i c protection & fe ed for w ar d lo g i c pr o t i ff vc - + - + 1 v s r q s r q uv l o uv lo pr o t r ff su pp ly & uv l o rfb rz cd rsense rcomp ccomp cr e f www.st.com
contents ALTAIR04-900 2/29 docid18211 rev 3 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 high voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 zero-current detection and triggering block . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 voltage feed-forward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 burst-mode operation (no load or very light load) . . . . . . . . . . . . . . . . . . 18 5.8 soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9 hiccup-mode ocp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.10 layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 test board: evaluation data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 test board: main waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
docid18211 rev 3 3/29 ALTAIR04-900 description 29 1 description this device combines two silicons in the same package: a low voltage pwm controller and a 900 v avalanche-rugged power section. the controller is in current-mode specifically designed for off-line quasi-resonant flyback converters. the device provides a constant output voltage using the primary-sensing feedback. this eliminates the need for the optocoupler, the secondary voltage reference, as well as the current sensor, still maintaining an accurate regulation. besides, the maximum deliverable output current can be set so to increase the end-product safety and reliability during fault events. quasi-resonant operation is guaranteed by a transformer demagnetization sensing input which turns on the power section. the same input also serves the output voltage monitoring, to perform cv regulation, and to achieve mains-independent maximum deliverable output current (line voltage feed-forward). the maximum switching frequency is top-limited 166 khz, so that at light-to-medium load a special function automatically lowers the operating frequency still maintaining the valley switching operation. when the load is very light, the device enters a controlled burst-mode operation that, along with the built-in high voltage start-up circuit and the low operating current, minimizes the standby power. although an auxiliary winding is required in the transformer to correctly perform cv/cc regulation, the chip powers itself directly from the rectified mains. this is important during cc regulation, where the flyback voltage, generated by the winding, drops below uvlo threshold. however, if ultra low no-load input consumption is required to comply with the most strict energy-saving recommendations, then the device needs to be powered by the auxiliary winding. these functions optimize power handling under different operating conditions. the device offers protection features that, in auto restart-mode, increase end-product safety and reliability: ? auxiliary winding disconnection, or brownout ? detection ? shorted secondary rectifier, or transformer saturation
pin connection ALTAIR04-900 4/29 docid18211 rev 3 2 pin connection figure 2. pin connection (top view) note: the copper area has to be placed under the drain pins to dissipate heat. n.a. n.a. source drain source gnd iref zcd/fb comp vcc drain drain drain n.a. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n.c. n.a. n.a. source drain source gnd iref zcd/fb comp vcc drain drain drain drain drain n.a. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n.c. n.a. table 1. pin functions number name function 1, 2 source power section source and input to the pwm comparator. the current, flowing through mosfet, is sensed by a resistor connected between the pin and gnd. the resulting voltage is compared with an internal reference (0.75 v max.) to determine the mosfet turn-off. the pin is equipped with 250 ns blanking time, after the gate-drive output goes high for noise immunity. if a second comparison level located at 1 v is exceeded the ic is stopped and restarted after vcc has dropped below 5 v. 3vcc supply voltage of the device. an electrolytic capacitor, connected between this pin and ground, is initially charged by the internal high voltage start-up generator; when the device runs, the same generator keeps it charged if the voltage, supplied by the auxiliary winding, is not sufficient. this feature is disabled if a protection is tripped. sometimes a small bypass capacitor (0.1 f typ.) to gnd might be useful to get a clean bias voltage for the signal part of ic. 4gnd ground. current return both for ic signal part and the gate-drive. all ground connections of bias components should be tied to a trace and kept separated from any pulsed current return. 5iref cc regulation loop reference voltage. an external capacitor has to be connected between this pin and gnd. an internal circuit develops a voltage on this capacitor used as the reference for peak drain current of the mosfet during cc regulation. the voltage is automatically adjusted to keep the average output current constant.
docid18211 rev 3 5/29 ALTAIR04-900 pin connection 29 6 zcd/fb transformer demagnetization sensing for quasi-resonant operation. input/output voltage monitoring. a negative-going edge triggers the mosfet turn-on. the current sourced by the pin during on-time is monitored to compensate the internal delay of the current sensing circuit and achieve a cc regulation independent of the mains voltage. if this current does not exceed 50 a, either a floating pin or a low input voltage is assumed, the device is stopped and restarted after vcc has dropped below 5 v. besides, the pin voltage is sampled-and-held right at the end of the transformer demagnetization to get an accurate image of the output voltage to be fed to the inverting input of the internal transconductance-type error amplifier, whose non-inverting input is 2.5 v. the maximum i zcd/fb sunk/sourced current doesn?t exceed 2 ma (amr) in all vin range conditions. no capacitor is allowed between the pin and the auxiliary transformer. 7comp output of the internal transconductance error amplifier. the compensation network is placed between this pin and gnd to achieve stability and good dynamic performance of the voltage control loop. 8-11 n.a not available. these pins must be left not connected. 12 n.c not internally connected. 13 to 16 drain drain connection of the internal power section. the internal high voltage start-up generator sinks current from these pins as well. pins are connected to the internal metal frame to facilitate heat dissipation. table 1. pin functions (continued) number name function
maximum ratings ALTAIR04-900 6/29 docid18211 rev 3 3 maximum ratings 3.1 absolute maximum ratings 3.2 thermal data table 2. absolute maximum ratings symbol pin parameter value unit v ds 1,2, 13-16 drain-to-source (ground) voltage -1 to 900 v i d 1,2, 13-16 drain current 0.7 a e av 1,2, 13-16 single pulse avalanche energy (t j = 25 c, i d = 0.7 a) 25 mj vcc 3 supply voltage (icc < 25 ma) self limiting v i zcd/fb 6 zero-current detector current 2 ma v comp 8 analog input -0.3 to 3.6 v p tot power dissipation @t a = 50 c 0.9 w t j junction temperature range -40 to 150 c t stg storage temperature -55 to 150 c table 3. thermal data symbol parameter max. value unit r thj-pin thermal resistance, junction-to-pin 10 c/w r thj-amb thermal resistance, junction-to-ambient 110
docid18211 rev 3 7/29 ALTAIR04-900 electrical characteristics 29 4 electrical characteristics (t j = -40 to 125 c, vcc = 14 v; unless otherwise specified) table 4. electrical characteristics symbol parameter test conditions min. typ. max. unit power section v (br)dss drain-source breakdown i d < 100 a; t j = 25 c 900 v i dss off-state drain current v ds = 850 v; t j = 125 c (see figure 4 and note) 80 a r ds(on) drain-source on-state resistance id=250 ma; t j = 25 c 16 19 ? id=250 ma; t j = 125 c 38 c oss effective (energy-related) output capacitance (see figure 3 ) high voltage start-up generator v start min. drain start voltage i charge < 100 a 40 50 60 v i charge vcc start-up charge current v drain > v start ; vcc < vcc on t j = 25 c 45.5 7 ma v drain > v start ; vcc < vcc on +/-10% v ccrestart vcc restart voltage (vcc falling) (1) 9.5 10.5 11.5 v after protection tripping 5 supply voltage vcc operating range after turn-on 11.5 23 v vcc on turn-on threshold (1) 12 13 14 v vcc off turn-off threshold (1) 91011v v z zener voltage icc = 20 ma 23 25 27 v supply current icc start-up start-up current (see figure 5 ) 200 300 a iq quiescent current (see figure 6 )11.4ma icc operating supply current @ 50 khz (see figure 7 )1.41.7ma iq (fault) fault quiescent current during hiccup and brownout (see figure 8 ) 250 350 a start-up timer t start start timer period 100 125 175 s t restart restart timer period during burst-mode 400 500 700 s
electrical characteristics ALTAIR04-900 8/29 docid18211 rev 3 zero-current detector i zcdb input bias current v zcd = 0.1 to 3 v 0.1 1 a v zcdh upper clamp voltage i zcd = 1 ma 3.0 3.3 3.6 v v zcdl lower clamp voltage i zcd = - 1 ma -90 -60 -30 mv v zcda arming voltage positive-going edge 100 110 120 mv v zcdt triggering voltage negative-going edge 50 60 70 mv i zcdon min. source current during mosfet on-time -25 -50 -75 a t blank trigger blanking time after mosfet turn-off v comp 1.3 v 6 s v comp = 0.9 v 30 line feed-forward r ff equivalent feed-forward resistor i zcd = 1 ma 45 transconductance error amplifier v ref voltage reference t j = 25 c (1) 2.46 2.5 2.54 v t j = -40 to 125 c and vcc = 12 v to 23 v (1) 2.42 2.58 gm transconductance i comp = 10 a v comp = 1.65 v 1.3 2.2 3.2 ms gv voltage gain open loop 73 db gb gain-bandwidth product 500 khz i comp source current v zcd = 2.3 v, v comp = 1.65 v 70 100 a sink current v zcd = 2.7 v, v comp = 1.65 v 400 750 a v comph upper comp voltage v zcd = 2.3 v 2.7 v v compl lower comp voltage v zcd = 2.7 v 0.7 v v compbm burst-mode threshold 1 v hys burst-mode hysteresis 65 mv current reference v irefx maximum value v comp = v compl (1) 1.5 1.6 1.7 v g i current loop gain v comp = v comph 0.5 0.6 0.7 v cref current reference voltage 0.38 0.4 0.42 v current sense t leb leading-edge blanking 200 250 300 ns t d(h-l) delay-to-output 300 ns v csx max. clamp value dvcs/dt = 200 mv/s (1) 0.7 0.75 0.8 v v csdis hiccup-mode ocp level (1) 0.92 1 1.08 v 1. parameters track one to each other table 4. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
docid18211 rev 3 9/29 ALTAIR04-900 electrical characteristics 29 figure 3. c oss output capacitance variation figure 4. off-state drain and source current test circuit note: the measured i dss is the sum between the current across the start-up resistor and the mosfet off-state drain current. figure 5. start-up current test circuit 0 25 50 75 100 125 150 0 100 200 300 400 500 c oss (pf) v ds (v) a iq(f ault) a idss 850 v 15v 2. 5v comp source drain vcc + - current control iref gnd fb/zcd 9 $ ,f fvw du wxs 9 &203 628 5& ( '5$,1 9ff &85 5(17 &21752/ ,5 () *1' )%=&'
electrical characteristics ALTAIR04-900 10/29 docid18211 rev 3 figure 6. quiescent current test circuit figure 7. operating supply current test circuit note: the circuit across the zcd pin is used for the switch-on synchronization. figure 8. quiescent current during fault test circuit 9 $ ,tbphdv 9 9 n 9 n 9 &203 6285 & ( '5 $, 1 9ff &85 5(17 &21752/ ,5() *1' )%=&' 9 n : $ ,ff 9 n n 9 n+ ] n n 9 9 &203 6285&( '5$,1 9ff &85 5(17 &21752/ ,5() *1' )%=&' 9 $ ,tidxow 9 &203 628 5& ( '5$,1 9ff &85 5(17 &21752/ ,5 () *1' )%=&'
docid18211 rev 3 11/29 ALTAIR04-900 application information 29 5 application information the device is an all-primary-sensing switching regulator, based on quasi-resonant flyback topology. according to the load conditions of the converter, the device can work in different modes (see figure 9 ): 1. qr-mode at heavy load. quasi-resonant operation synchronizes mosfet turn-on and the demagnetization of the transformer by detecting the resulting negative-going edge of the voltage across any winding of the transformer. the system works close to the boundary between discontinuous (dcm) and continuous conduction (ccm) of the transformer. therefore, the switching frequency is different according to different line/load conditions (see the hyperbolic-like portion of the curves in figure 9 ). minimum turn-on losses, low emi emissions and safe behavior in short-circuit are the main benefits of this operation. 2. valley-skipping-mode at light-to-medium load. according to voltage on comp pin, the device defines the maximum operating frequency of the converter. as the load is reduced, mosfet turn-on doesn?t occur on the first valley but on the second one, the third one and so on. in this manner, the switching frequency doesn?t rise (piecewise linear portion in figure 9 ). 3. burst-mode with or without very light load. when the load is extremely light or disconnected, the converter enters a controlled on/off operation with a constant peak current. decreasing the load results even few hundred hertz minimizes all frequency- related losses and makes it easier to comply with energy saving regulations or recommendations. being the peak current very low, no issue of audible noise arises. figure 9. multi-mode operation of the ALTAIR04-900 0 f sw pinmax input voltage p in f osc burst-mode valley-skipping mode quasi-resonant mode 0 f sw pinmax input voltage p in f osc burst-mode valley-skipping mode quasi-resonant mode 0 f sw pinmax input voltage p in f osc burst-mode valley-skipping mode quasi-resonant mode
application information ALTAIR04-900 12/29 docid18211 rev 3 5.1 power section and gate driver the power section guarantees the safe avalanche operation within the specified energy rating as well as high dv/dt capability. the mosfet has a v (br)dss of 900 v min. and a typical r ds(on) of 16 . the gate driver is designed to supply a controlled gate current during both turn-on and turn- off in order to minimize common-mode emi. under uvlo conditions, an internal pull-down circuit holds the gate low in order to ensure that the mosfet cannot be turned on accidentally. 5.2 high voltage start-up generator figure 10 shows the internal schematic of the high voltage start-up generator (hv generator). the hv current generator is supplied through the drain pin and it is enabled only if the input bulk capacitor voltage is higher than v start threshold, 50 v dc typically. when the hv current generator is on, the i charge current (5.5 ma typical value) is delivered to the capacitor on the vcc pin. with reference to the timing diagram in figure 10 , when power is applied to the circuit and the voltage on the input bulk capacitor is high, the hv generator is sufficiently biased to start operating, thus it draws about 5.5 ma (typical) from the bulk capacitor. this current charges the bypass capacitor connected between the vcc pin and ground and rises its voltage linearly. as the vcc voltage reaches the start-up threshold (13 v typ.) the chip starts operating, the internal mosfet is enabled to switch and the hv generator is cut off by the vcc_ok signal asserted high. the ic is powered by the energy stored in the vcc capacitor. the chip powers itself directly from the rectified mains: when the voltage on the vcc pin falls below vcc restart (10.5v typ.), during each mosfet off-time, the hv current generator turns on and charges the supply capacitor until it reaches the vcc on threshold. in this manner, the self-supply circuit develops a high voltage to sustain the operation of the device. this feature is useful during cc regulation, when the flyback voltage generated by the auxiliary winding alone, may not be able to keep vcc above vcc restart . at converter power-down, the system loses regulation as soon as the input voltage falls below v start . this avoids converter restart attempts and assures monotonic output voltage decay at system power-down.
docid18211 rev 3 13/29 ALTAIR04-900 application information 29 figure 10. timing diagram: normal power-up and power-down sequences 5.3 zero-current detection and triggering block the zero-current detection (zcd) and triggering blocks switch on the mosfet if a negative-going edge falling below 50 mv is applied to the zcd/fb pin. the triggering block must be previously armed by a positive-going edge exceeding 100 mv. this feature detects transformer demagnetization for qr operation, where the signal for zcd input is obtained by the transformer auxiliary winding, also used to supply the ic. figure 11. zcd block, triggering block the triggering block is blanked after mosfet turn-off to prevent any negative-going edge, following leakage inductance demagnetization, from triggering the zcd circuit erroneously. this blanking time is dependent on the voltage on comp pin: it is t blank = 30 s for v comp = 0.9 v, and decreases almost linearly down to t blank = 6 s for v comp = 1.3 v. the voltage on the pin is both top and bottom-limited by a double clamp, as illustrated in the internal diagram of zcd block (see figure 11 ). the upper clamp is typically 3.3 v, while the lower clamp is -60 mv. the interface between the pin and the auxiliary winding is a resistor vcc drain vcc on vcc resta rt t t t t vin v st a rt i cha rg e 5.5 ma t t power-on power-off nor m a l op er a tion cv mode cc mode norm al op er a tion vcc drain vcc on vcc resta rt t t t t vin v st a rt i cha rg e 5.5 ma t t power-on power-off nor m a l op er a tion cv mode cc mode norm al op er a tion 60 m v zcd clamp b l an kin g ti me tu r n - o n logi c star ter s r q leb + - aux rf b rzcd to d riv er from cc /cv block from ocp zcd/ f b 110mv
application information ALTAIR04-900 14/29 docid18211 rev 3 divider. its resistance ratio as well as the individual resistance values have to be properly chosen (see ? section 5.4: constant voltage operation ? and ? section 5.6: voltage feed- forward block ?). the maximum i zcd/fb sunk/sourced current must not exceed 2 ma (amr) in all vin range conditions. no capacitor is allowed between zcd pin and the auxiliary transformer. the switching frequency is 166 khz top-limited, as the converter operating frequency can increase excessively at light load and on high input voltage. a starter block is also used to start up the system, that is, to turn on the mosfet during the converter power-up, when any or a very small signal is available on zcd pin. the starter frequency is 2 khz if comp pin is below burst-mode threshold, 1 v, while it becomes 8 khz if this voltage exceeds this value. after the first few cycles initiated by the starter, as the voltage developed across the auxiliary winding arms the zcd circuit, mosfet turn-on starts to be locked to transformer demagnetization, hence setting up qr operation. the starter is also active when the ic is in cc regulation and the output voltage is not so high to allow the zcd triggering. if the demagnetization completes, hence a negative-going edge appears on zcd pin, after a time exceeding t blank time, the mosfet turns on again, with some delay to assure minimum voltage at turn-on. if, instead, the negative-going edge appears before t blank has elapsed, it is ignored and the first negative-going edge after t blank turns on the mosfet. therefore one or more drain ringing cycles are skipped (?valley-skipping-mode?, figure 12 ) and the switching frequency cannot exceed 1/t blank . figure 12. drain ringing cycle skipping as the load is progressively reduced when the system operates in valley-skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the mosfet changes with discrete steps of one ringing cycle, while the off-time needed for cycle-by- cycle energy balance may fall in between. thus one or more longer switching cycles are compensated by one or more shorter cycles and vice versa. however, this mechanism is absolutely normal and there is no appreciable impact on the performance of the converter or on its output voltage. p in = p in' ( limit co ndi ti on) p in = p in'' < p in' p in = p in''' < p in'' t v ds t fw t osc t v t on t v ds t osc t v ds t o sc
docid18211 rev 3 15/29 ALTAIR04-900 application information 29 5.4 constant voltage operation the ic is specifically designed to work in the primary regulation and the output voltage is sensed through a voltage partition of the auxiliary winding, just before the auxiliary rectifier diode. figure 13 shows the internal schematic of the constant voltage-mode and the external connections. figure 13. voltage control principle: internal schematic due to the parasitic wire resistance, the auxiliary voltage is representative of the output just when the secondary current becomes zero. for this purpose, the signal on zcd/fb pin is sampled-and-held at the end of the transformer demagnetization to get an accurate image of the output voltage and it is compared with the error amplifier internal reference. the comp pin is used for the frequency compensation: usually, an rc network, which stabilizes the overall voltage control loop, is connected between this pin and ground. the output voltage can be defined according to the following formula: equation 1 where n sec and n aux are the numbers of secondary and auxiliary turns respectively. r zcd value depends on the application parameters (see ? section 5.6: voltage feed-forward block ?). 2. 5v rzcd f rom rsense aux + - ea r to pwm logic s/ h rf b demag logi c + - cv c comp zcd/fb r fb v ref n aux n sec -------------- v out v ref ? ? ------------------------------------------------------ r zcd ? =
application information ALTAIR04-900 16/29 docid18211 rev 3 5.5 constant current operation figure 14 presents the principle used to control the average output current of a flyback converter. the output voltage of the auxiliary winding is used by the demagnetization block to generate the control signal for the switch q1. r resistor absorbs a current v c /r, where v c is the voltage developed across the capacitor c ref . the flip-flop output is high as long as the transformer delivers current on the secondary side. this is shown in figure 15 . the capacitor c ref has to be chosen so that its voltage v c can be considered as a constant. since it is charged and discharged by currents in the range of 10 a (i cref is typically 20 a) at the switching frequency rate, a capacitance value in the range of 4.7-10 nf suits to switching frequencies of 10 khz. the average output current can be expressed as follows: equation 2 where n pri is the primary turn number. this formula shows that the average output current does not depend neither on the input or the output voltage, nor on transformer inductance values. the external parameters defining the output current, are the transformer ratio n and the sense resistor r sense . g i current loop gain and v cref current reference voltage are internally defined. figure 14. current control principle i out n pri n sec ------------- - g i v cref ? 2r sense ? () -------------------------------- - ? = . iref rzcd rfb aux q1 ir ef r gi demag logi c to pwm logic from rsense zcd/fb + - cc c s r q
docid18211 rev 3 17/29 ALTAIR04-900 application information 29 figure 15. constant current operation: switching cycle waveforms 5.6 voltage feed-forward block the current control structure uses the voltage v c to define the output current, according to equation 2. actually, the cc comparator is affected by t d an internal propagation delay, which switches off the mosfet with a peak current higher than the foreseen value. this current overshoot is equal to: equation 3 where l p is the primary inductance and it introduces an error on the calculated cc set point, depending on the input voltage. the device implements a line feed-forward function, which solves the issue by introducing an input offset voltage on the current sense signal, in order to adjust the cycle-by-cycle current limitation. the internal schematic is shown in figure 16 . t t t t i p i s q i c t r v i c cref ? = cref i in d p p vt ? i l ? =
application information ALTAIR04-900 18/29 docid18211 rev 3 figure 16. feed-forward compensation: internal schematic r zcd resistor can be calculated as follows: equation 4 the peak drain current does not depend on the input voltage. concerning r zcd value: during the mosfet on-time, the current, sourced from zcd/fb pin, i zcd , is compared with an internal reference current i zcdon (-50atypical). if i zcd < i zcdon , the brownout function is active and ic shuts down. this feature is important when the auxiliary winding is accidentally disconnected and considerably increases the end-product safety and reliability. 5.7 burst-mode operation (no load or very light load) when the voltage on comp pin falls 65 mv below a fixed threshold, v compbm , the ic is disabled, the mosfet is in off-state and its consumption reduced to a lower value to minimize vcc capacitor discharge. due to this condition, the converter operates in burst-mode (one pulse train every t start = 500 s), with a minimum energy transfer. therefore, the output voltage decreases: after 500 s the controller switches on the mosfet again and the sampled voltage on the zcd pin is compared with the internal reference. if the voltage on the ea output, as a result of the comparison, exceeds the v compl threshold, the device restarts switching, otherwise it is off for another period of 500 s. the converter works in burst-mode with a nearly constant peak current. a load decrease causes a frequency reduction, which can go down even to few hundreds hertz, thus minimizing all frequency-related losses and meeting energy saving regulations. this kind of operation, shown in the timing diagrams (see figure 17 ) along with the others previously described, is noise-free since the peak current is low. . cc block aux r zcd rfb iff rsense rff + - cc feedforward logic pwm logi c zcd/fb drain source aux p ff zcd pri d sense nlr r ntr ? =? ?
docid18211 rev 3 19/29 ALTAIR04-900 application information 29 figure 17. load-dependent operating modes: timing diagrams 5.8 soft-start and starter block the soft-start feature is automatically implemented by the constant current block, as the primary peak current is limited on the c ref capacitor. during the startup, as the output voltage is zero, ic starts in cc-mode without high peak current operations. the voltage on the output capacitor increases slowly and the soft-start feature is assured. actually the c ref value is not important to define the soft-start time, as its duration depends on other circuit parameters, such as: transformer ratio, sense resistor, output capacitors and load. the user can define the best appropriate value. com p i ds 65 mv hyster. normal-mode burst-mode normal-mode t sta r t t start t start t st ar t v co mpl
application information ALTAIR04-900 20/29 docid18211 rev 3 5.9 hiccup-mode ocp the device is also protected against short-circuit of the secondary rectifier, short-circuit on the secondary winding or a hard-saturated flyback transformer. a comparator monitors continuously the voltage on r sense and activates a protection circuitry if this voltage exceeds 1 v. to distinguish a malfunction from a disturbance (induced during esd tests), the first time the comparator is tripped, the protection circuit enters a ?warning state?. if in the following switching cycle the comparator is not tripped, a temporary disturbance is assumed and the protection logic is reset in its idle state; if the comparator is tripped again a real malfunction is assumed and the device stops. this condition is latched as long as the device is supplied. any energy comes from the self- supply circuit; hence the voltage on the vcc capacitor decays and crosses the uvlo threshold after some time, which clears the latch. the internal start-up generator is still off, then the vcc voltage still needs to go below its restart voltage before the vcc capacitor is charged again and the device restarted. finally, this results in a low-frequency intermittent operation (hiccup-mode operation), with very low stress on the power circuit. this special condition is illustrated in the timing diagram of figure 18 . figure 18. hiccup-mode ocp: timing diagram v ds vc c on vc c of f vcc rest secondary diode is shorted here t t t v sou rce 1 v two switching cycles v cc vcs dis
docid18211 rev 3 21/29 ALTAIR04-900 application information 29 5.10 layout recommendations a proper printed circuit board layout is very important for the correct operation of any switch- mode converter. placing components carefully, routing traces correctly, appropriate trace widths and compliance with isolation distances are very important matters. in particular: ? the compensation network should be connected as closer as possible to the comp pin, keeping short the trace for the gnd ? signal ground should be routed separately from power ground, as well as from the sense resistor trace figure 19. suggested routing for the converter $ &,1 28 7 *1 ' &203 628 5&( '5 $, 1 9ff ,5() *1 ' )% =&' $/7$,5 $ &,1
typical applications ALTAIR04-900 22/29 docid18211 rev 3 6 typical applications figure 20. test board schematic: 4.5 w (9 v - 500 ma) wide range mains adapter figure 21. electrical schematic for 440 v ac input voltage option due to 900 v rated power section of the ALTAIR04-900 )7 5 . & x) / x) %5 5 n & q) 5 n & x) 9 7 & x ) & ) 5 . ' 6736/ 5 5 . & x) 9 ' 1 & x) & q) & q) <& $3 5 : & q) & q) & q) ' 677+/ 5 n 5 / x+ 9 ( & 5 8 2 6 3 0 2 & '5 $,1 9ff &855(17 &21 752/ ,5() *1 ' )%=&' 8 $/7$,5 *1' $&,1 $&,1 9$ *1' 6736/$ ' & q) 75 1& 5 q) < &$3 & . 5 ' 3.($ ) $ 59 9 & q) ; p+ / 9 &203 6285& ( '5 $,1 9ff &855 (17 &21752/ ,5 () *1' )%=& ' 8 $/7 $,5 5 . 5 677+ ' & q) & x) . 5 3' '%/6*5' n 5 & x) 9 6736 ' 9$ & q) & q) $&, 1 & x) $&, 1 ' 6736 5 & x) 1& 5 n 5 &0 / x+ q) & x) & ,1 *1' 287 4 /)$% x) & 9$ & q) ; & x) 9 17& rkp : 5 0 5 0 17& rkp :
docid18211 rev 3 23/29 ALTAIR04-900 typical applications 29 6.1 test board: evaluation data figure 22. no-load consumption figure 23. efficiency at full load ,qsxw3rzhu>p:@ '&,qsxw9rowdjh>9@ (iilflhqf\>@ $&,qsxw9rowdjh>9 $& @ figure 24. v-i curve @ 110 v ac figure 25. v-i curve @ 264 v ac 2xwsxw9rowdjh>9@ 2xwsxw&xuuhqw>p$@ 2xwsxw9rowdjh>9@ 2xwsxw&xuuhqw>p$@
typical applications ALTAIR04-900 24/29 docid18211 rev 3 6.2 test board: main waveforms figure 26. 110 v ac , no-load m: 400 s/div figure 27. 264 v ac , no-load m: 400 s/div figure 28. 110 v ac , full load m: 400 s/div figure 29. 234 v ac , full load m: 400 s/div
docid18211 rev 3 25/29 ALTAIR04-900 package mechanical data 29 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 30. so16n drawings b*
package mechanical data ALTAIR04-900 26/29 docid18211 rev 3 figure 31. so16n footprint table 5. so16n mechanical data dim. mm typ. min. max. a 1.55 1.43 1.68 a1 0.15 0.12 0.18 a2 1.52 1.48 1.56 b 0.40 0.375 0.425 c 0.238 d 9.85 9.82 9.88 e 6.00 5.90 6.10 e1 3.90 3.87 3.93 e1.27 h 0.425 0.50 l 0.635 0.585 0.685 k 428 ccc 0.04
docid18211 rev 3 27/29 ALTAIR04-900 ordering information 29 8 ordering information table 6. ordering information order codes package packaging ALTAIR04-900 so16n tube ALTAIR04-900tr tape and reel
revision history ALTAIR04-900 28/29 docid18211 rev 3 9 revision history table 7. document revision history date revision changes 11-nov-2010 1 initial release 25-jan-2011 2 updated chapter table 4. on page 7 07-oct-2014 3 updated table 2: absolute maximum ratings , section 4: electrical characteristics and section 7: package mechanical data . minor text changes.
docid18211 rev 3 29/29 ALTAIR04-900 29 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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